Circuits that store data, such as a latch circuit or a flip-flop circuit, may cause an erroneous operation due to inversion of a stored data value. This inversion is caused by incidence of a radiation of heavy particles or the like which are present in a cosmic space. This phenomenon will be described using a latch circuit formed of two inverter circuits of a CMOS type as an example.
Assume that in the latch circuit shown in FIG. 9, an inverter circuit 101 first outputs a low level, and an inverter circuit 102 outputs a high level. At this point, a P-channel transistor 103 is in an on state, while an N-channel transistor 104 is in an off state. When a radiation (of heavy particles) enters a drain of the N-channel transistor 104, a current 105 flows from the drain to a substrate (ground). This current 105 is supplied as a current 106 through the P-channel transistor 103 in the on state. Since the P-channel transistor 103 has an on resistance, a voltage drop occurs at a drain of the P-channel transistor 103 due to flow of the current 106. That is, a voltage at a node 107 drops. The larger energy received from the heavy particles which have entered the drain of the N-channel transistor 104, the larger a magnitude of the current 105 (=a magnitude of the current 106) increases. As a result, a drop range of the voltage at the node 107 increases.
When a voltage change at the node 107 at a time of incidence of the radiation to the inverter circuit 102 exceeds a threshold voltage of an input to the inverter circuit 101 connected to the node 107, a voltage at a node 108, which is an output of the inverter circuit 101, is inverted from a low level to a high level. When the voltage at the node 108 is inverted, a value input to an input terminal of the inverter circuit 102 connected to the node 108 is also inverted from the low level to the high level. This inverts an output of the inverter circuit 102 from the high level to the low level. That is, when a magnitude of the energy received from the radiation that has entered the inverter circuit 102 exceeds a certain level, a value latched at the latch circuit will be inverted, thereby causing an erroneous operation.
In the above description, an explanation was given, assuming that the inverter circuit 101 outputs the low level, and the inverter 102 outputs the high level. However, when the inverter circuit 101 outputs the high level, the inverter circuit 102 outputs the low level, and the heavy particles enter the drain of the P-channel transistor 103 in the off state as well, the same phenomenon occurs. In this case, a current flows through an on resistance of the N-channel transistor 104 in the on state, and the voltage at the node 107 increases. Then, the value latched by the latch circuit will be inverted, thereby causing an erroneous operation.
When a semiconductor integrated circuit device is used in the cosmic space or the like, the erroneous operation as described above will become a great problem. Then, in the semiconductor integrated circuit device used in the cosmic space or the like, it is necessary to set tolerance of the semiconductor integrated circuit device to radiation to be larger than that of a common semiconductor integrated circuit so as not to cause any erroneous operation even when the radiation of the heavy particles or the like enters. As a method of improving tolerance of a latch circuit to radiation, a method of adding resistance to the latch circuit (resistance-added latch circuit of the resistive decoupling type) is described in Non-patent Document 1. In the resistance-added latch circuit, a resistance is inserted between an output of an inverter circuit and an input to an inverter circuit in a next stage. Since the resistance is inserted, a waveform of an input voltage is more rounded (a peak value of the waveform is reduced) than when the resistance is not added. Accordingly, a voltage change peak value caused by incidence of radiation is reduced by the input to the inverter circuit in the next stage. The voltage change peak value does not reach a threshold (threshold) value. For this reason, the value latched by the latch circuit will not be inverted.
In the resistance-added latch circuit as described above, the waveform is rounded by addition of the resistance in an ordinary operation of the latch circuit. It is therefore difficult to operate the circuit at high speed. Then, a technique that forms a circuit which has high tolerance to irradiation of radiation while operating at high speed is disclosed in Patent Document 1. In a latch circuit described in Patent Document 1, a hysteresis circuit is added to an input to a logic circuit, thereby increasing a threshold voltage of the latch circuit. Accordingly, even when a radiation enters, inclusion of noise induced by the radiation into an input in the next stage can be prevented by the increased threshold voltage, and inversion of a value latched by the latch circuit can be thereby prevented. Since rounding of the waveform is not generated at a time of the normal operation, the circuit can be operated at high speed.
[Non-Patent Document 1]
J. L. Andrews, “SINGLE EVENT ERROR IMMUNE CMOS RAM”, IEEE Transactions on Nuclear Science, Vol. NS-29, No. 6, pp. 2040-2043, December 1982
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2005-341354A (FIG. 4)